1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to a method of manufacturing the liquid crystal display device.
2. Discussion of the Related Art
A liquid crystal display (LCD) device is driven based on the optical anisotropy and polarization characteristics of a liquid crystal material. In general, the LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode, and the electrodes of each substrate are also facing each other. Voltage is applied to each electrode, and thus an electric field is induced between the electrodes. Alignment of the liquid crystal molecules is changed by the varying intensity or direction of the electric field. The LCD device displays a picture by varying transmittance of the light according to the arrangement of the liquid crystal molecules.
An active matrix liquid crystal display (AMLCD) device, which includes thin film transistors as a switching device for a plurality of pixels, has been widely used due to its high resolution and fast moving images.
A related art LCD device will be described hereafter in detail with reference to figures.
FIG. 1 is a schematic solid view illustrating a related art LCD device. In the LCD device, upper and lower substrates 10 and 30 are spaced apart from and facing each other, and a liquid crystal layer 50 is interposed between the upper substrate 10 and the lower substrate 30.
At least one gate line 32 and at least one data line 34 are formed on the inner surface of the lower substrate 30 (i.e., the side facing the upper substrate 10). The gate line 32 and the date line 34 cross each other to define a pixel region P. A thin film transistor T, as a switching element, is formed at the crossing of the gate line 32 and the data line 34. Although not shown in detail in the figure, the thin film transistor T includes a gate electrode, a source electrode, a drain electrode, and an active layer. A plurality of such thin film transistors T is arranged in a matrix form to correspond to other crossings of gate and data lines. A pixel electrode 46, which is connected to the thin film transistor T, is formed in the pixel region P.
The upper substrate 10 includes a black matrix 14, a color filter layer 12, and a common electrode 16 subsequently on the inside (i.e., the side facing the lower substrate 30). The color filter layer 12 reflects light in a specific wavelength range and includes three sub-color filters of red (R), green (G), and blue (B). The black matrix 14 is disposed between the sub-color filters, and blocks light in an area where liquid crystal molecules are not controlled. Each sub-color filter of the color filter layer 12 corresponds to the pixel electrode 46 at the pixel region P.
Upper and lower polarizers 52 and 54, each of which may be a linear polarizer that transmits only linearly polarized light parallel to its light transmission axis, are arranged over outer surfaces of the upper and lower substrates 10 and 30, respectively. In addition, a backlight is disposed over the outer surface of the lower polarizer 54 as a light source.
The lower substrate 30, which includes the thin film transistors T and the pixel electrodes 46 arranged in the matrix form, may be commonly referred to as an array substrate.
FIG. 2 illustrates a plan view of an array substrate for an LCD device according to the related art. In FIG. 2, a gate line 64 is formed in a first direction and a data line 78 is formed in a second direction crossing the first direction. The gate line 64 and the data line 78 cross each other and define a pixel region P. A thin film transistor T is formed as a switching element at the crossing of the gate and data lines 64 and 78. A pixel electrode 94 is formed in the pixel region P. The thin film transistor T includes a gate electrode 62 that is connected to the gate line 64 and receives scanning signals, a source electrode 74 that is connected to the data line 78 and receives data signals, and a drain electrode 76 that is spaced apart from the source electrode 74. The thin film transistor T further includes an active layer 72 between the gate electrode 62 and the source and drain electrodes 74 and 76. The pixel electrode 94 is connected to the thin film transistor T by contacting the drain electrode 76.
A metal pattern 88 of an island shape overlaps the gate line 64. The metal pattern 88 is made of the same material as the data line 78. The pixel electrode 94 also overlaps the gate line 64, and is connected to the metal pattern 88. Thus, the gate line 64 and the metal pattern 88 form a storage capacitor CST with an insulating layer (not shown) interposed therebetween, wherein the overlapped gate line 64 acts as a first electrode of the storage capacitor CST and the metal pattern 88 functions as a second electrode of the storage capacitor CST.
Additionally, a gate pad 68 is formed at one end of the gate line 64, and a data pad 82 is formed at one end of the data line 78. A gate pad terminal 96 and a data pad terminal 98, which have an island shape and are made of the same material as the pixel electrode 94, overlap the gate pad 68 and the data pad 82, respectively.
FIGS. 3A to 3E, FIGS. 4A to 4E, and FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing an array substrate according to the related art. FIGS. 3A to 3E correspond to cross-sections along the line III-Ill′ of FIG. 2, FIGS. 4A to 4E correspond to cross-sections along the line IV-IV′ of FIG. 2, and FIGS. 5A to 5E correspond to cross-sections along the line V-V′ of FIG. 2.
As illustrated in FIGS. 3A, 4A and 5A, a gate line 64, a gate electrode 62 and a gate pad 68 are formed on a transparent insulating substrate 60 by depositing a first metal layer and patterning the first metal layer through a first mask process that is a photolithography process utilizing photo-resist and a mask. Although not shown in the figures, the gate electrode 62 is extended from the gate line 64 and the gate pad 68 is disposed at one end of the gate line 64.
As illustrated in FIGS. 3B, 4B and 5B, a first insulating layer, an amorphous silicon layer, a doped amorphous silicon layer are subsequently deposited on the substrate 60 including the gate line 64, the gate electrode 62 and the gate pad 68 thereon, and the doped amorphous silicon layer and the amorphous silicon layer are patterned through a second mask process. Thus, a doped amorphous silicon pattern 73a and active layer 72 are formed over the gate electrode 62. The first insulating layer acts as a gate insulating layer 70.
As illustrated in FIGS. 3C, 4C and 5C, a data line 78, a source electrode 74, a drain electrode 76, a metal pattern 80 and a data pad 82 are formed on the substrate 60 including the doped amorphous silicon layer 73a of FIG. 3B and the active layer 72 thereon by depositing a second metal layer and patterning it through a third mask process. The source and drain electrodes 74 and 76 are disposed over the active layer 72, spaced apart. The metal pattern 80 partially overlaps the gate line 64. Although not shown in the figures, the data line 78 crosses the gate line 64 and the data pad 82 is disposed at one end of the data line 78.
Next, the doped amorphous silicon layer 73a of FIG. 3B exposed between the source and drain electrodes 74 and 76 is removed. Thus, an ohmic contact layer 73 is completed and the active layer 72 is exposed. An exposed portion of the active layer 72 becomes a channel ch of a thin film transistor T, which includes the gate electrode 62, the source electrode 74, the drain electrode 76, and the active layer 72.
As illustrated in FIGS. 3D, 4D and 5D, a second insulating layer is formed on the substrate 60 including the thin film transistor T thereon and is patterned with the gate insulating layer 70 through a fourth mask process, thereby forming a passivation layer 84 that has a drain contact hole 86, a capacitor contact hole 88, a gate pad contact hole 90 and a data pad contact hole 92. The drain contact hole 86, the capacitor contact hole 88, the gate pad contact hole 90 and the data pad contact hole 92 expose the drain electrode 76, the metal pattern 80, the gate pad 68 and the data pad 82, respectively.
Next, as illustrated in FIGS. 3E, 4E and 5E, a pixel electrode 94, a gate pad terminal 96 and a data pad terminal 98 are formed on the passivation layer 84 by depositing a transparent conductive material and patterning the transparent conductive material through a fifth mask process. The pixel electrode 94 is connected to not only the drain electrode 76 via the drain contact hole 86 but also to the metal pattern 80 through the capacitor contact hole 88. The gate pad terminal 96 is connected to the gate pad 68 via the gate pad contact hole 90 and the data pad terminal 98 is connected to the data pad 82 through the data pad contact hole 92. The pixel electrode 94 is formed in the pixel region P. The gate line 64 and the metal pattern 80, which overlap each other, form a storage capacitor CST with the gate insulating layer 70 interposed between the gate line 64 and the metal pattern 80.
The array substrate is manufactured through five mask processes, and the mask process includes several steps of cleaning, coating a photo-resist layer, exposing through a mask, developing the photo-resist layer, and etching. Therefore, fabricating time, costs, and failure may be decreased by reducing the number of the photolithography processes.